1. FIELD OF THE INVENTION
The present invention relates to a distributed sensing control circuit for a sense amplifier of memory devices suitable for an integrated memory device.
2. DESCRIPTION OF THE PRIOR ART
As the memory density becomes higher, the number of sense amplifier circuits increases and total charge to be handled within a cycle becomes larger, which causes peak currents to rise, and signal voltages of bit lines and a sensing speed to lower. Consequently, the reliability of a memory device is degraded. The circuit arrangement of the prior art will be described with reference to FIG. 1.
A NMOS sensing control transistor M.sub.1 and a PMOS sensing control transistor M.sub.2 are connected to a precharge circuit PC. Each sense amplifier SA.sub.1, SA.sub.2, . . ., SA.sub.n through each parasitic resistance R is connected in common with N and P MOS sensing control transistors M.sub.1 and M.sub.2, wherein the individual sense amplifier has the circuit arrangement, as shown in FIG. 4, in which the section "a" has a NMOS sense amplifier and the section "b" has a P MOS sense amplifier. The sensing control transistors M.sub.1 and M.sub.2 have gates through which sensing control signals LA, LA from an external sense amplifier control circuit (not shown) are applied. The resistance R is a parasitic resistance resulted from a layout, and the value of resistance is small, typically about 5.OMEGA..
In the prior circuit arrangement with the type of aforesaid configuration, the sensing control transistors M.sub.1 and M.sub.2, by LA, LA signal, control the multiple of sensing amplifiers SA.sub.1 -SA.sub.n, so that the value of currents varying with time di/dt increases because the peak currents Iccl and Issl, respectively (see FIG. 6), of the power supply line of V.sub.cc and V.sub.ss have a sharp increment when sensing nodes (S, S) are charged and discharged at each V.sub.cc, V.sub.ss through the sensing control transistors M.sub.1, M.sub.2.
Therefore, the component of inductance in the power supply line of V.sub.cc and V.sub.ss causes noises in V.sub.cc and V.sub.ss (V.sub.n =L di/dt, where V.sub.n is noise voltages, L is inductance), and the signal voltage of the bit line and the sensing speed decrease with the operation of sense amplifiers.
The number of sense amplifiers to be connected to the sensing control transistors M.sub.1 and M.sub.2 increases with the increase of memory density. Accordingly, the total current through M.sub.1 and M.sub.2 transistors becomes larger. This slows down the sensing speed because it takes long time to discharge the sense amplifier voltage.